In order to convert the D flip flop into an actual one-bit registry, we must go through a few additional steps. In order to do this, we must have a way to load and save the data into it. For this, on the one hand, we must have a method to only load whatever data on the data line into the registry on the next clock pulse. On the other hand, we must only store the data back into the data line.
However, before we continue the project, we must have a test clock pulse. This is because the project will need an asynchronous clock to work. This can be done easily by modifying the clock module we had before. The only thing we must do is select the astable pulse, reset the manual pulse and reset the halt signal. In the end, we will send a clock pulse into the module. In the final product, we will not have this module in place.
module test_clock (clk);
reg apulse, select, mpulse, hlt;
output clk;
initial apulse = 1;
initial select = 1; // Selecting astable pulse
initial mpulse = 0; // Resetting manual pulse
initial hlt = 0; // Resetting halt signal
clock test(apulse, select, mpulse, hlt, clk);
always begin
#2 apulse = ~apulse;
#2 apulse = ~apulse;
end
endmodule
Structure of a One-bit register
If the load signal is low, We're feeding the existing value back into the flip flop. On the other hand, if we have the load signal high, we're loading the new data value into the flip flop.
Implementing this in Verilog is straightforward.
module bit_register(clk, input_enable, output_enable, data, out);
input clk, input_enable, data;
output out;
wire not_out;
wire buf_out;
wire mem_data;
assign mem_data = (buf_out && ~input_enable) || (input_enable && data);
d_flip_flop flip_memory (clk, mem_data, buf_out, not_out);
endmodule
However, we can't stop here. The issue is that in this design, we're outputting the data back into the data line all the time. However, the data line will have multiple registers connected thus, the data must only get output when required. So we must also have an output_enable wire and a way to send data into the line only when output_enable is high.
What we require is a Tri-state Buffer. In a buffer, high or low data is output into the data wire only if the enable wire is high. If it is low, we keep this wire in a floating state. Thus, whatever data any other register is sending back into the data wire will be accepted instead of overriding it with this register.
Building a buffer is also quite simple.
module buffer(data, enable, out);
input data, enable;
output reg out;
always @* begin
if (enable == 1) begin
out <= data;
end
else begin
out <= 1'bZ;
end
end
endmodule
What we do is send the data line back to the data lane if enable is high. If not, we send 1'bZ (Float) to the line.
Output Waveform
With this, we have a complete One-bit register.
One-bit register with tri-state buffer
module bit_register(clk, input_enable, output_enable, data, out);
input clk, input_enable, output_enable, data;
output out;
wire not_out;
wire buf_out;
wire mem_data;
assign mem_data = (buf_out && ~input_enable) || (input_enable && data);
d_flip_flop flip_memory (clk, mem_data, buf_out, not_out);
buffer buf_memory (buf_out, output_enable, out);
endmodule
One-bit Register
External Links:
- Base video: Designing and building a 1-bit register - 8 bit register - Part 3
- Github Repo: Eight-Bit Computer using FPGA