To have the memory functionalities in a computer, one of the most important components is to have a way to store data within a memory unit. For this, one of the best ways is to use a D Flip Flop. A D Flip Flop is a component that can store one bit of information.
In his video, Ben Eater designs a D Flip Flop using logic gates.
First, we will start with a D Latch.
D Latch Design
This works by sending an output of one NOR gate to another NOR gate as input. This way, the input received by the flip flop stays within itself, until one of the inputs is changed. This is done by setting the other input of each NOR gate from the data input. To simplify this operation, we introduce an AND gate. This AND gate will only return 1 if both the data input and enable input to go high. So depending on whether we need to set the memory to 1 or 0, we can use two such gates. Both will receive the same enable input while one of them will receive a negated input of the data input. This way, if enabled, the relevant AND gate will output a 1 depending on whether we want to store a 1 or a 0. Sending this output to the relevant NOR gate will complete this operation.
Implementing this in Verilog is quite easy. We first need to create the module with two inputs and two outputs: enable as the enable input, data as the data input, Q as the stored memory and not_Q as the inverse of Q. In addition to these, we will also need two wires feedback1 and feedback2. These two wires will help implement the feedback loops. Then it is a matter of implementing the logic gates.
module d_flip_flop (enable, data, Q, not_Q);
input enable, data;
output Q, not_Q;
wire feedback1, feedback2;
assign feedback1 = ~((~(data) && enable) || feedback2);
assign feedback2 = ~((data && enable) || feedback1);
assign Q = feedback1;
assign not_Q = feedback2;
endmodule
Then we must move on to the testbench which is also relatively easy. For this we need two registers: enable and data. First, we set enable as 1 and data as 0. At this point, the output Q must be low. Next, we set the data bit to 1. As we're already in the enable state, the output Q must switch to 1. Then we move on to set the enable to 0 and data also to 0. Since now we're not enabled, the last stored 1 value must continue to be there. However, as soon as we switch enable to 1, the stored bit must switch to 0. The ~Q output must always be the exact opposite of Q.
Output waveform of the testbench
With this, we have a memory module. However, now we have to convert this to a D Flip Flop. This is as simple as replacing enable with clk and adding a check for the positive edge of the clk.
module d_flip_flop (clk, data, Q, not_Q);
input clk, data;
output Q, not_Q;
wire feedback1, feedback2;
reg a;
assign feedback1 = ~((~(a)) || feedback2);
assign feedback2 = ~((a) || feedback1);
always @(posedge clk)
begin
a <= data;
end
assign Q = feedback1;
assign not_Q = feedback2;
endmodule
With this, we can conclude the D Flip Flop.
The D Flip Flop
External Links:
- Base video: D flip-flop
- Github Repo: Eight-Bit Computer using FPGA